/**
 ******************************************************************************
 * @file    dma.h
 * @author  hyseim software Team
 * @date    22-Mar-2024
 * @brief   This file provides all the headers of the dmac functions.
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DMA_H__
#define __DMA_H__

#ifdef __cplusplus
extern "C"
{
#endif
/* Includes ------------------------------------------------------------------*/
#include "chip_define.h"
#include "typedefine.h"
#include "common.h"

    /** @addtogroup WB32F11x_StdPeriph_Driver
     * @{
     */

    /** @addtogroup DMAC
     * @{
     */

    /* Exported types ------------------------------------------------------------*/

#if 1
    /* start input to im110gw.h*/
    /* ================================================================================ */
    /* ==============        Direct Memory Access Controller (DMAC)       ============= */
    /* ================================================================================ */
    typedef struct
    {
        __I uint32_t IDAR;       /*!< DMAC ID and Revision Register               Address offset: 0x0  */
        __I uint32_t IDMR;       /*!< DMAC ID Misc Register                       Address offset: 0x4  */
        uint32_t RESERVED0[2];   /*!< Reserved                                    Address offset: 0x8  */
        __I uint32_t CFGR;       /*!< DMAC Configuration Register                 Address offset: 0x10 */
        uint32_t RESERVED1[3];   /*!< Reserved                                    Address offset: 0x14 */
        __O uint32_t SOFT_RESET; /*!< DMAC Control Register                       Address offset: 0x20 */
        __O uint32_t ABT;        /*!< Channel Abort Register                      Address offset: 0x24 */
        uint32_t RESERVED2[2];   /*!< Reserved                                    Address offset: 0x28 */
        __IO uint32_t ISR;       /*!< Interrupt Status Register                   Address offset: 0x30 */
        __I uint32_t CESR;       /*!< Channel Enable Status Register              Address offset: 0x34 */
        uint32_t RESERVED3[2];   /*!< Reserved                                    Address offset: 0x38 */
        struct
        {
            __IO uint32_t CCR;       /*!< Channel n Control Register                           Address offset: 0x40 + n*0x20  */
            __IO uint32_t CTSR;      /*!< Channel n Transfer Size Register                     Address offset: 0x44 + n*0x20  */
            __IO uint32_t CSAR;      /*!< Channel n The Source Starting Address Register       Address offset: 0x48 + n*0x20  */
            __IO uint32_t RESERVED4; /*!< Reserved                                             Address offset: 0x4C + n*0x20  */
            __IO uint32_t CDAR;      /*!< Channel n The Destination Starting Address Register  Address offset: 0x50 + n*0x20  */
            __IO uint32_t RESERVED5; /*!< Reserved                                             Address offset: 0x54 + n*0x20  */
            __IO uint32_t CLLPR;     /*!< Channel n Linked List Pointer Register               Address offset: 0x58 + n*0x20  */
            __IO uint32_t RESERVED6; /*!< Reserved                                             Address offset: 0x5C + n*0x20  */
        } Chx[8];                    /*!< DMAH_NUM_CHANNELS is 8 */
    } DMAC_t;

    typedef struct
    {
        __IO uint32_t CCR;       /*!< Channel n Control Register                           Address offset: 0x00 */
        __IO uint32_t CTSR;      /*!< Channel n Transfer Size Register                     Address offset: 0x04 */
        __IO uint32_t CSAR;      /*!< Channel n The Source Starting Address Register       Address offset: 0x08 */
        __IO uint32_t RESERVED0; /*!< Reserved                                             Address offset: 0x0C */
        __IO uint32_t CDAR;      /*!< Channel n The Destination Starting Address Register  Address offset: 0x10 */
        __IO uint32_t RESERVED1; /*!< Reserved                                             Address offset: 0x14 */
        __IO uint32_t CLLPR;     /*!< Channel n Linked List Pointer Register               Address offset: 0x18 */
        __IO uint32_t RESERVED2; /*!< Reserved                                             Address offset: 0x1C */
    } LinkList_t __attribute__((aligned(8)));

/*------------------------------------------------------------------------------------------------------*/
/*---                             Direct Memory Access Controller (DMAC)                             ---*/
/*------------------------------------------------------------------------------------------------------*/
/*******************************  Bit definition for DMAC Control Register  *******************************/
#define DMAC_SOTF_RESET (0x1 << 0) /*!< Software reset control. Write 1 to this bit to reset \
                                                the DMA core and disable all channels. */

/*******************************  Bit definition for Channel Abort Register  *******************************/
#define DMAC_CH0_ABORT (0x1 << 0) /*!< Write 1 to bit 0 to abort channel 0. */
#define DMAC_CH1_ABORT (0x1 << 1) /*!< Write 1 to bit 1 to abort channel 1. */
#define DMAC_CH2_ABORT (0x1 << 2) /*!< Write 1 to bit 2 to abort channel 2. */
#define DMAC_CH3_ABORT (0x1 << 3) /*!< Write 1 to bit 3 to abort channel 3. */
#define DMAC_CH4_ABORT (0x1 << 4) /*!< Write 1 to bit 4 to abort channel 4. */
#define DMAC_CH5_ABORT (0x1 << 5) /*!< Write 1 to bit 5 to abort channel 5. */
#define DMAC_CH6_ABORT (0x1 << 6) /*!< Write 1 to bit 6 to abort channel 6. */
#define DMAC_CH7_ABORT (0x1 << 7) /*!< Write 1 to bit 7 to abort channel 7. */

/*******************************  Bit definition for Interrupt Status Register  *******************************/
#define DMAC_CH0_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 0 to clear transfer finish interrupt flag channel 0. */
#define DMAC_CH1_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 1 to clear transfer finish interrupt flag channel 1. */
#define DMAC_CH2_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 2 to clear transfer finish interrupt flag channel 2. */
#define DMAC_CH3_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 3 to clear transfer finish interrupt flag channel 3. */
#define DMAC_CH4_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 4 to clear transfer finish interrupt flag channel 4. */
#define DMAC_CH5_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 5 to clear transfer finish interrupt flag channel 5. */
#define DMAC_CH6_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 6 to clear transfer finish interrupt flag channel 6. */
#define DMAC_CH7_INT_TC_FLAG (0x1 << 16) /*!< Write 1 to bit 7 to clear transfer finish interrupt flag channel 7. */

#define DMAC_CH0_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 0 to clear transfer abort interrupt flag channel 0. */
#define DMAC_CH1_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 1 to clear transfer abort interrupt flag channel 1. */
#define DMAC_CH2_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 2 to clear transfer abort interrupt flag channel 2. */
#define DMAC_CH3_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 3 to clear transfer abort interrupt flag channel 3. */
#define DMAC_CH4_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 4 to clear transfer abort interrupt flag channel 4. */
#define DMAC_CH5_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 5 to clear transfer abort interrupt flag channel 5. */
#define DMAC_CH6_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 6 to clear transfer abort interrupt flag channel 6. */
#define DMAC_CH7_INT_ABORT_FLAG (0x1 << 8) /*!< Write 1 to bit 7 to clear transfer abort interrupt flag channel 7. */

#define DMAC_CH0_INT_ERROR_FLAG (0x1 << 0) /*!< Write 1 to bit 0 to clear transfer error interrupt flag channel 0. */
#define DMAC_CH1_INT_ERROR_FLAG (0x1 << 1) /*!< Write 1 to bit 1 to clear transfer error interrupt flag channel 1. */
#define DMAC_CH2_INT_ERROR_FLAG (0x1 << 2) /*!< Write 1 to bit 2 to clear transfer error interrupt flag channel 2. */
#define DMAC_CH3_INT_ERROR_FLAG (0x1 << 3) /*!< Write 1 to bit 3 to clear transfer error interrupt flag channel 3. */
#define DMAC_CH4_INT_ERROR_FLAG (0x1 << 4) /*!< Write 1 to bit 4 to clear transfer error interrupt flag channel 4. */
#define DMAC_CH5_INT_ERROR_FLAG (0x1 << 5) /*!< Write 1 to bit 5 to clear transfer error interrupt flag channel 5. */
#define DMAC_CH6_INT_ERROR_FLAG (0x1 << 6) /*!< Write 1 to bit 6 to clear transfer error interrupt flag channel 6. */
#define DMAC_CH7_INT_ERROR_FLAG (0x1 << 7) /*!< Write 1 to bit 7 to clear transfer error interrupt flag channel 7. */

/*******************************  Bit definition for Channel Enable Status Register  *******************************/
#define DMAC_CH0_ENABLE_STAT (0x1 << 0) /*!< show channel 0 enable status. */
#define DMAC_CH1_ENABLE_STAT (0x1 << 1) /*!< show channel 1 enable status. */
#define DMAC_CH2_ENABLE_STAT (0x1 << 2) /*!< show channel 2 enable status. */
#define DMAC_CH3_ENABLE_STAT (0x1 << 3) /*!< show channel 3 enable status. */
#define DMAC_CH4_ENABLE_STAT (0x1 << 4) /*!< show channel 4 enable status. */
#define DMAC_CH5_ENABLE_STAT (0x1 << 5) /*!< show channel 5 enable status. */
#define DMAC_CH6_ENABLE_STAT (0x1 << 6) /*!< show channel 6 enable status. */
#define DMAC_CH7_ENABLE_STAT (0x1 << 7) /*!< show channel 7 enable status. */

/*******************************  Bit definition for Channel n Control Register  *******************************/
#define DMAC_CCR_CHx_RELOAD (0x1U << 31) /*!< Channel reload field */
#define DMAC_CCR_CHx_PRIOR (0x1U << 29)  /*!< Channel priority field */

#define DMAC_CCR_CHx_SRC_MSIZE_1 (0x0U << 24)   /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_2 (0x1U << 24)   /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_4 (0x2U << 24)   /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_8 (0x3U << 24)   /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_16 (0x4U << 24)  /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_32 (0x5U << 24)  /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_64 (0x6U << 24)  /*!< Source Burst Transaction Length */
#define DMAC_CCR_CHx_SRC_MSIZE_128 (0x7U << 24) /*!< Source Burst Transaction Length */

#define DMAC_CCR_CHx_SRC_TFR_WIDTH_8 (0x0U << 21)  /*!< Source Transfer Data Width is 8 bits */
#define DMAC_CCR_CHx_SRC_TFR_WIDTH_16 (0x1U << 21) /*!< Source Transfer Data Width is 16 bits */
#define DMAC_CCR_CHx_SRC_TFR_WIDTH_32 (0x2U << 21) /*!< Source Transfer Data Width is 32 bits */

#define DMAC_CCR_CHx_DST_TFR_WIDTH_8 (0x0U << 18)  /*!< Destination Transfer Data Width is 8 bits */
#define DMAC_CCR_CHx_DST_TFR_WIDTH_16 (0x1U << 18) /*!< Destination Transfer Data Width is 16 bits */
#define DMAC_CCR_CHx_DST_TFR_WIDTH_32 (0x2U << 18) /*!< Destination Transfer Data Width is 32 bits */

#define DMAC_CCR_CHx_M2M_DMAC (0x0U << 16) /*!< Transfer Type is Memory to Memory, Flow Control is DMAC */
#define DMAC_CCR_CHx_M2P_DMAC (0x1U << 16) /*!< Transfer Type is Memory to Peripheral, Flow Control is DMAC */
#define DMAC_CCR_CHx_P2M_DMAC (0x2U << 16) /*!< Transfer Type is Peripheral to Memory, Flow Control is DMAC */
#define DMAC_CCR_CHx_P2P_DMAC (0x3U << 16) /*!< Transfer Type is Peripheral to Peripheral, Flow Control is DMAC */

#define DMAC_CCR_CHx_SINC_INC (0x0U << 14) /*!< Source Address Increment is increment */
#define DMAC_CCR_CHx_SINC_DEC (0x1U << 14) /*!< Source Address Increment is decrement */
#define DMAC_CCR_CHx_SINC_NO (0x2U << 14)  /*!< Source Address Increment is no change */

#define DMAC_CCR_CHx_DINC_INC (0x0U << 12) /*!< Destination Address Increment is increment */
#define DMAC_CCR_CHx_DINC_DEC (0x1U << 12) /*!< Destination Address Increment is decrement */
#define DMAC_CCR_CHx_DINC_NO (0x2U << 12)  /*!< Destination Address Increment is no change */

#define DMAC_CCR_CHx_SRC_REQ_SEL (0x8U) /*!< Source DMA request select. */
#define DMAC_CCR_CHx_DST_REQ_SEL (0x4U) /*!< Destination DMA request select. */

#define DMAC_CCR_CHx_DISABLE (0x0U << 0) /*!<  Channel disable */
#define DMAC_CCR_CHx_ENALBE (0x1U << 0)  /*!<  Channel enable */
/*end input to im110gw.h*/
#endif

    /**
     * @brief  DMAC Channel Init Structure definition
     */
    typedef struct
    {
        FunctionalState_t DMAC_Reload;                      /*!< Specifies the automatic source reload feature enable or not.
                                                                This parameter can be: ENABLE or DISABLE. */
        uint8_t DMAC_ChannelPriority;                       /*!< Specifies Channel priority level. 0x0:Lower priority, 0x1:Higher priority.*/
        uint32_t DMAC_SrcBurstTransactionLength;            /*!< Specifies the source burst transaction length.
                                                                This parameter can be a value of @ref DMAC_SrcBurstTransactionLength.
                                                                @note This parameter has no effect if the source is memory. */
        uint32_t DMAC_SrcTfrDataWidth;                      /*!< Specifies the source transfer data width.
                                                                This parameter can be a value of @ref DMAC_SRC_TFR_WIDTH. */
        uint32_t DMAC_DstTfrDataWidth;                      /*!< Specifies the destination transfer data width.
                                                                This parameter can be a value of @ref DMAC_DST_TFR_WIDTH. */
        uint32_t DMAC_TransferDirection;                    /*!< Specifies if the data will be transferred from memory to memory,from memory to peripheral,
                                                                from peripheral to memory or from peripheral to peripheral.
                                                                This parameter can be a value of @ref DMAC_TransferDirection. */
        uint32_t DMAC_SrcAddrInc;                           /*!< Specifies whether to increment or decrement or no_change address the source address on every source transfer.
                                                                This parameter can be a value of @ref DMAC_SrcAddrInc. */
        uint32_t DMAC_DstAddrInc;                           /*!< Specifies whether to increment or decrement  or no_change address the destination address on every destination transfer.
                                                                This parameter can be a value of @ref DMAC_DstAddrInc. */
        uint8_t DMAC_SrcHardwareHandshakingInterfaceAssign; /*!< Specifies the hardware handshaking interface to the source of this channel if
                                                                the configuration DMAC_SourceHandshakingInterfaceSelect is DMAC_SourceHandshakingInterfaceSelect_Hardware.
                                                                This parameter can be a value of @ref DMAC_HardwareHandshakingInterface. */
        uint8_t DMAC_DstHardwareHandshakingInterfaceAssign; /*!< Specifies the hardware handshaking interface to the source of this channel if
                                                                the configuration DMAC_DestinationHandshakingInterfaceSelect is DMAC_DestinationHandshakingInterfaceSelect_Hardware.
                                                                This parameter can be a value of @ref DMAC_HardwareHandshakingInterface. */
        uint32_t DMAC_BlockTransferSize;                    /*!< Specifies the block transfer size when the DMAC is the flow controller, in data unit.
                                                                The data unit is equal to the configuration set in DMAC_SourceTransferWidth.
                                                                This parameter can be a number between 1 and 0xffffffff. */
        uint32_t DMAC_SrcAddress;                           /*!< Specifies Current Source Address of DMA transfer.
                                                                @note the SAR address to be aligned to DMAC_SRC_TFR_WIDTH */
        uint32_t DMAC_DstAddress;                           /*!< Specifies Current Destination address of DMA transfer.
                                                                @note the DAR to be aligned to DMAC_DST_TFR_WIDTH */
    } DMAC_ChannelInit_t;

/* Exported constants --------------------------------------------------------*/

/** @defgroup DMAC_Exported_Constants
 * @{
 */

/** @defgroup DMAC_SRC_TFR_WIDTH
 * @{
 */
#define DMAC_SRC_TFR_WIDTH_8bits DMAC_CCR_CHx_SRC_TFR_WIDTH_8
#define DMAC_SRC_TFR_WIDTH_16bits DMAC_CCR_CHx_SRC_TFR_WIDTH_16
#define DMAC_SRC_TFR_WIDTH_32bits DMAC_CCR_CHx_SRC_TFR_WIDTH_32
/**
 * @}
 */

/** @defgroup DMAC_DST_TFR_WIDTH
 * @{
 */
#define DMAC_DST_TFR_WIDTH_8bits DMAC_CCR_CHx_DST_TFR_WIDTH_8
#define DMAC_DST_TFR_WIDTH_16bits DMAC_CCR_CHx_DST_TFR_WIDTH_16
#define DMAC_DST_TFR_WIDTH_32bits DMAC_CCR_CHx_DST_TFR_WIDTH_32
/**
 * @}
 */

/** @defgroup DMAC_SrcAddrInc
 * @{
 */
#define DMAC_SrcAddrInc_Increment DMAC_CCR_CHx_SINC_INC
#define DMAC_SrcAddrInc_Decrement DMAC_CCR_CHx_SINC_DEC
#define DMAC_SrcAddrInc_NoChange DMAC_CCR_CHx_SINC_NO
/**
 * @}
 */

/** @defgroup DMAC_DstAddrInc
 * @{
 */
#define DMAC_DstAddrInc_Increment DMAC_CCR_CHx_DINC_INC
#define DMAC_DstAddrInc_Decrement DMAC_CCR_CHx_DINC_DEC
#define DMAC_DstAddrInc_NoChange DMAC_CCR_CHx_DINC_NO
/**
 * @}
 */

/** @defgroup DMAC_SrcBurstTransactionLength
 * @{
 */
#define DMAC_SrcBurstTransactionLength_1 DMAC_CCR_CHx_SRC_MSIZE_1
#define DMAC_SrcBurstTransactionLength_2 DMAC_CCR_CHx_SRC_MSIZE_2
#define DMAC_SrcBurstTransactionLength_4 DMAC_CCR_CHx_SRC_MSIZE_4
#define DMAC_SrcBurstTransactionLength_8 DMAC_CCR_CHx_SRC_MSIZE_8
#define DMAC_SrcBurstTransactionLength_16 DMAC_CCR_CHx_SRC_MSIZE_16
#define DMAC_SrcBurstTransactionLength_32 DMAC_CCR_CHx_SRC_MSIZE_32
#define DMAC_SrcBurstTransactionLength_64 DMAC_CCR_CHx_SRC_MSIZE_64
#define DMAC_SrcBurstTransactionLength_128 DMAC_CCR_CHx_SRC_MSIZE_128
/**
 * @}
 */

/** @defgroup DMAC_TransferDirection
 * @{
 */
#define DMAC_TransferDirection_M2M DMAC_CCR_CHx_M2M_DMAC
#define DMAC_TransferDirection_M2P DMAC_CCR_CHx_M2P_DMAC
#define DMAC_TransferDirection_P2M DMAC_CCR_CHx_P2M_DMAC
#define DMAC_TransferDirection_P2P DMAC_CCR_CHx_P2P_DMAC
/**
 * @}
 */

/** @defgroup DMAC_AutoReload
 * @{
 */
#define DMAC_AutoReload_Enable (DMAC_CCR_CHx_RELOAD)
#define DMAC_AutoReload_Disable (0x0U << 31)
/**
 * @}
 */

/** @defgroup DMA Handshaking Interface Signal Mux Configure offset
 * @{
 */
#define HANDSHAKING_MAX_NUM (0x10)
#define ADDR_CFG_SOC_CON4 (0x030)
#define ADDR_CFG_SOC_CON5 (0x034)
#define ADDR_CFG_SOC_CON6 (0x038)
#define ADDR_CFG_SOC_CON7 (0x03c)
/**
 * @}
 */

/** @defgroup DMAC_HardwareHandshakingInterface
 * @{
 */
/* ASSI => UART */
#define DMA_HS_UART0_DMA_TX (0U)
#define DMA_HS_UART0_DMA_RX (1U)
#define DMA_HS_UART1_DMA_TX (2U)
#define DMA_HS_UART1_DMA_RX (3U)
#define DMA_HS_UART2_DMA_TX (4U)
#define DMA_HS_UART2_DMA_RX (5U)
#define DMA_HS_UART3_DMA_TX (6U)
#define DMA_HS_UART3_DMA_RX (7U)
#define DMA_HS_UART4_DMA_TX (8U)
#define DMA_HS_UART4_DMA_RX (9U)
#define DMA_HS_UART5_DMA_TX (10U)
#define DMA_HS_UART5_DMA_RX (11U)
#define DMA_HS_UART6_DMA_TX (12U)
#define DMA_HS_UART6_DMA_RX (13U)
#define DMA_HS_UART7_DMA_TX (14U)
#define DMA_HS_UART7_DMA_RX (15U)
/* ASSI => I2C */
#define DMA_HS_I2C0_DMA_TX (0U)
#define DMA_HS_I2C0_DMA_RX (1U)
#define DMA_HS_I2C1_DMA_TX (2U)
#define DMA_HS_I2C1_DMA_RX (3U)
#define DMA_HS_I2C2_DMA_TX (4U)
#define DMA_HS_I2C2_DMA_RX (5U)
#define DMA_HS_I2C3_DMA_TX (6U)
#define DMA_HS_I2C3_DMA_RX (7U)
#define DMA_HS_I2C4_DMA_TX (8U)
#define DMA_HS_I2C4_DMA_RX (9U)
#define DMA_HS_I2C5_DMA_TX (10U)
#define DMA_HS_I2C5_DMA_RX (11U)
#define DMA_HS_I2C6_DMA_TX (12U)
#define DMA_HS_I2C6_DMA_RX (13U)
#define DMA_HS_I2C7_DMA_TX (14U)
#define DMA_HS_I2C7_DMA_RX (15U)
/* ASSI => MSPI */
#define DMA_HS_MSPI0_DMA_TX (0U)
#define DMA_HS_MSPI0_DMA_RX (1U)
#define DMA_HS_MSPI1_DMA_TX (2U)
#define DMA_HS_MSPI1_DMA_RX (3U)
#define DMA_HS_MSPI2_DMA_TX (4U)
#define DMA_HS_MSPI2_DMA_RX (5U)
#define DMA_HS_MSPI3_DMA_TX (6U)
#define DMA_HS_MSPI3_DMA_RX (7U)
#define DMA_HS_MSPI4_DMA_TX (8U)
#define DMA_HS_MSPI4_DMA_RX (9U)
#define DMA_HS_MSPI5_DMA_TX (10U)
#define DMA_HS_MSPI5_DMA_RX (11U)
#define DMA_HS_MSPI6_DMA_TX (12U)
#define DMA_HS_MSPI6_DMA_RX (13U)
#define DMA_HS_MSPI7_DMA_TX (14U)
#define DMA_HS_MSPI7_DMA_RX (15U)
/* ASSI => SSPI */
#define DMA_HS_SSPI0_DMA_TX (0U)
#define DMA_HS_SSPI0_DMA_RX (1U)
#define DMA_HS_SSPI1_DMA_TX (2U)
#define DMA_HS_SSPI1_DMA_RX (3U)
#define DMA_HS_SSPI2_DMA_TX (4U)
#define DMA_HS_SSPI2_DMA_RX (5U)
#define DMA_HS_SSPI3_DMA_TX (6U)
#define DMA_HS_SSPI3_DMA_RX (7U)
#define DMA_HS_SSPI4_DMA_TX (8U)
#define DMA_HS_SSPI4_DMA_RX (9U)
#define DMA_HS_SSPI5_DMA_TX (10U)
#define DMA_HS_SSPI5_DMA_RX (11U)
#define DMA_HS_SSPI6_DMA_TX (12U)
#define DMA_HS_SSPI6_DMA_RX (13U)
#define DMA_HS_SSPI7_DMA_TX (14U)
#define DMA_HS_SSPI7_DMA_RX (15U)
/* trig_mux use */
#define DMA_HS_TRIG_DMAMUX0 (16U)
#define DMA_HS_TRIG_DMAMUX1 (17U)
#define DMA_HS_TRIG_DMAMUX2 (18U)
#define DMA_HS_TRIG_DMAMUX3 (19U)
/**
 * @}
 */

/** @defgroup DMAC_channel
 * @{
 */
#define DMAC_Channel_0 ((uint8_t)0x0)
#define DMAC_Channel_1 ((uint8_t)0x1)
#define DMAC_Channel_2 ((uint8_t)0x2)
#define DMAC_Channel_3 ((uint8_t)0x3)
#define DMAC_Channel_4 ((uint8_t)0x4)
#define DMAC_Channel_5 ((uint8_t)0x5)
#define DMAC_Channel_6 ((uint8_t)0x6)
#define DMAC_Channel_7 ((uint8_t)0x7)
/**
 * @}
 */

/** @defgroup DMAC_interrupts_definitions
 * @{
 */
#define DMAC_IT_TFR_TRIG ((uint8_t)0x1) /* Transfer complete interrupt */
#define DMAC_IT_ERR_TRIG ((uint8_t)0x2) /* Error interrupt */
#define DMAC_IT_ABT_TRIG ((uint8_t)0x3) /* Transfer abort interrupt */
/**
 * @}
 */

/** @defgroup DMAC_interrupts_definitions
 * @{
 */
#define DMAC_IT_TFR_ISR ((uint8_t)0x10) /* Transfer complete interrupt flag*/
#define DMAC_IT_ABT_ISR ((uint8_t)0x8)  /* Transfer abort interrupt flag*/
#define DMAC_IT_ERR_ISR ((uint8_t)0x0)  /* Error interrupt flag*/
/**
 * @}
 */

/** @defgroup DMAC_DEBUG Macro
 * @{
 */
#define DEBUG 0
/**
 * @}
 */

/**
 * @}
 */

/* Exported macro ------------------------------------------------------------*/
#define DMAC0 ((DMAC_t *)(DMAC_BASE))
#if DEBUG
#define DMA_PRINT(format, ...) printf("[DMA]Line:%d,Function:%s-->" format "", __LINE__, __func__, ##__VA_ARGS__)
#else
#define DMA_PRINT(format, ...)
#endif

/* Exported functions ------------------------------------------------------- */
void DMAC_ChannelStructDefaultInit(DMAC_ChannelInit_t *DMAC_ChannelInitStruct);
void DMAC_ChannelInit(DMAC_t *DMACx, uint8_t DMAC_Channel, DMAC_ChannelInit_t *DMAC_ChannelInitStruct);
void DMAC_ChannelSetSourceAddress(DMAC_t *DMACx, uint8_t DMAC_Channel, uint32_t SourceAddress);
void DMAC_ChannelSetDestinationAddress(DMAC_t *DMACx, uint8_t DMAC_Channel, uint32_t DestinationAddress);
void DMAC_ChannelSetBlockTransferSize(DMAC_t *DMACx, uint8_t DMAC_Channel, uint32_t DMAC_BlockTransferSize);
uint32_t DMAC_ChannelGetBlockTransferSize(DMAC_t *DMACx, uint8_t DMAC_Channel);
void DMAC_ChannelAbortCmd(DMAC_t *DMACx, uint8_t DMAC_Channel, FunctionalState_t NewState);

/* Configuration and Channel Enable functions *********************************/
void DMAC_ChannelCmd(DMAC_t *DMACx, uint8_t DMAC_Channel, FunctionalState_t NewState);
void DMAC_ChannelCmdWithReload(DMAC_t *DMACx, uint8_t DMAC_Channel, FunctionalState_t NewState);
FunctionalState_t DMAC_GetChannelCmdStatus(DMAC_t *DMACx, uint8_t DMAC_Channel);

/* Interrupts management functions ********************************************/
void DMAC_ITConfig(DMAC_t *DMACx, uint8_t DMAC_Channel, uint8_t DMAC_IT, FunctionalState_t NewState);
void DMAC_ITConfigWithReload(DMAC_t *DMACx, uint8_t DMAC_Channel, uint8_t DMAC_IT, FunctionalState_t NewState);
ITStatus_t DMAC_GetITStatus(DMAC_t *DMACx, uint8_t DMAC_Channel, uint8_t DMAC_IT);
void DMAC_ClearITBit(DMAC_t *DMACx, uint8_t DMAC_Channel, uint8_t DMAC_IT);

/* HardwareHandshakingInterface get mux number functions ********************************************/
void DMAC_InitHardwareHandshakingInterfaceMux(void);
uint8_t DMAC_GetHardwareHandshakeNumber(uint8_t HardwareHandshakingInterface);

/**
 * @}
 */

/**
 * @}
 */

#ifdef __cplusplus
}
#endif
#endif
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